The present invention relates generally to memory systems. More specifically, the invention provides a divisible true dual port (TDP) memory system supporting simple dual port (SDP) memory subsystems. Merely by way of example, the invention has been applied to field-programmable gate arrays (FPGAs), but it would be recognized that the invention has a much broader range of applicability.
An FPGA system often includes an embedded memory system. The embedded memory system can be used to provide various types of memory functions. The memory functions include, for example, those of first-in-first-out memory (FIFO), read-only memory (ROM), and random-access memory (RAM). As RAM, the embedded memory system can be configured to support different types of operation modes. The operation modes may include true dual port (TDP), simple dual port (SDP), and single port (SP). A TDP memory system can support two writes, one read and one write, or two reads at one time. Besides having two independent in/out (IO) data paths and address decoders, the TDP memory system includes two independent write bit-lines drivers and sense amplifiers to support two writes or two reads simultaneously. In contrast, a SDP memory system can support one read and one write at the same time. The SDP memory system can be built from a TDP memory system by using one particular port to write and the other to read.
For example, a conventional 8K TDP SRAM memory includes 256 rows and 32 columns of dual port RAM cells. Each column of the RAM cells is accessible through Port A and Port B differential bit-lines with their respective Port A and Port B write drivers, sense amplifiers, and column and row decoder circuitry. For TDP operation, two-read, one-read and one-write, or two-write operations can be performed simultaneously. For SDP operation, one read and one write can be performed simultaneously. Port A is used as write port, and port B is used as read port.
The conventional SRAM system usually cannot be divided effectively into several SRAM sub-systems. Hence it is desirable to improve techniques for memory systems.